/*
 * Copyright (C) 2018 Unigroup Spreadtrum & RDA Technologies Co., Ltd.
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 * updated at 2018-12-18 10:53:49
 *
 */


#ifndef ANLG_PHY_G14_H
#define ANLG_PHY_G14_H

#define CTL_BASE_ANLG_PHY_G14 0x32408000


#define REG_ANLG_PHY_G14_ANALOG_PCIE_GEN2_1T1R_ANA_PCIE31_CTRL0      ( CTL_BASE_ANLG_PHY_G14 + 0x0000 )
#define REG_ANLG_PHY_G14_ANALOG_PCIE_GEN2_1T1R_ANA_PCIE31_CTRL1      ( CTL_BASE_ANLG_PHY_G14 + 0x0004 )
#define REG_ANLG_PHY_G14_ANALOG_PCIE_GEN2_1T1R_ANA_PCIE31_CTRL2      ( CTL_BASE_ANLG_PHY_G14 + 0x0008 )
#define REG_ANLG_PHY_G14_ANALOG_PCIE_GEN2_1T1R_ANA_PCIE31_CTRL3      ( CTL_BASE_ANLG_PHY_G14 + 0x000C )
#define REG_ANLG_PHY_G14_ANALOG_PCIE_GEN2_1T1R_REG_SEL_CFG_0         ( CTL_BASE_ANLG_PHY_G14 + 0x0010 )

/* REG_ANLG_PHY_G14_ANALOG_PCIE_GEN2_1T1R_ANA_PCIE31_CTRL0 */

#define BIT_ANLG_PHY_G14_ANALOG_PCIE_GEN2_1T1R_PIPE_BIST_EN            BIT(2)
#define BIT_ANLG_PHY_G14_ANALOG_PCIE_GEN2_1T1R_PIPE_BIST_DONE          BIT(1)
#define BIT_ANLG_PHY_G14_ANALOG_PCIE_GEN2_1T1R_PIPE_BIST_OK            BIT(0)

/* REG_ANLG_PHY_G14_ANALOG_PCIE_GEN2_1T1R_ANA_PCIE31_CTRL1 */

#define BIT_ANLG_PHY_G14_ANALOG_PCIE_GEN2_1T1R_PIPE_RESET_N            BIT(15)
#define BIT_ANLG_PHY_G14_ANALOG_PCIE_GEN2_1T1R_PIPE_TRIM_TXRCTL(x)     (((x) & 0xF) << 11)
#define BIT_ANLG_PHY_G14_ANALOG_PCIE_GEN2_1T1R_PIPE_TRIM_RXRCTL(x)     (((x) & 0xF) << 7)
#define BIT_ANLG_PHY_G14_ANALOG_PCIE_GEN2_1T1R_PIPE_TRIM_BG(x)         (((x) & 0xF) << 3)
#define BIT_ANLG_PHY_G14_ANALOG_PCIE_GEN2_1T1R_PIPE_PS_PD_S            BIT(2)
#define BIT_ANLG_PHY_G14_ANALOG_PCIE_GEN2_1T1R_PIPE_PS_PD_L            BIT(1)
#define BIT_ANLG_PHY_G14_ANALOG_PCIE_GEN2_1T1R_PIPE_ISO_SW_EN          BIT(0)

/* REG_ANLG_PHY_G14_ANALOG_PCIE_GEN2_1T1R_ANA_PCIE31_CTRL2 */

#define BIT_ANLG_PHY_G14_ANALOG_PCIE_GEN2_1T1R_PIPE_TOUT_0             BIT(3)
#define BIT_ANLG_PHY_G14_ANALOG_PCIE_GEN2_1T1R_PIPE_TOUT_1             BIT(2)
#define BIT_ANLG_PHY_G14_ANALOG_PCIE_GEN2_1T1R_PIPE_TOUT_2             BIT(1)
#define BIT_ANLG_PHY_G14_ANALOG_PCIE_GEN2_1T1R_PIPE_TOUT_3             BIT(0)

/* REG_ANLG_PHY_G14_ANALOG_PCIE_GEN2_1T1R_ANA_PCIE31_CTRL3 */

#define BIT_ANLG_PHY_G14_ANALOG_PCIE_GEN2_1T1R_PIPE_RESERVEDIN(x)      (((x) & 0xFFFF) << 16)
#define BIT_ANLG_PHY_G14_ANALOG_PCIE_GEN2_1T1R_PIPE_RESERVEDOUT(x)     (((x) & 0xFFFF))

/* REG_ANLG_PHY_G14_ANALOG_PCIE_GEN2_1T1R_REG_SEL_CFG_0 */

#define BIT_ANLG_PHY_G14_DBG_SEL_ANALOG_PCIE_GEN2_1T1R_PIPE_RESET_N    BIT(3)
#define BIT_ANLG_PHY_G14_DBG_SEL_ANALOG_PCIE_GEN2_1T1R_PIPE_PS_PD_S    BIT(2)
#define BIT_ANLG_PHY_G14_DBG_SEL_ANALOG_PCIE_GEN2_1T1R_PIPE_PS_PD_L    BIT(1)
#define BIT_ANLG_PHY_G14_DBG_SEL_ANALOG_PCIE_GEN2_1T1R_PIPE_ISO_SW_EN  BIT(0)


#endif /* ANLG_PHY_G14_H */


